This invention relates to logic arrays capable of being programmed during fabrication as an integrated circuit device, and more particularly to a programmable logic array (PLA) which uses parallel transistor logic gates arranged in a compact layout for fast signal propagation, and which is prechargable.
A PLA 10, as shown on a small scale in FIG. 1, is a general purpose circuit which is later customized or programmed to perform predefined logical sum-of-product functions. A PLA is programmed by arranging for desired subsets of its input signals I1 through IM to be logically multiplied by a row of AND gates, known as the "AND plane," to produce logical product terms T1 through TP known as "minterms," and further by arranging for desired subsets of the P minterms to be logically added by a column of OR gates, known as the "OR plane," to produce logical sum (of product) PLA output terms Z1 through ZN. The sum-of-product signals Z1 through ZN may be fed pack to other PLA input lines for sequential operations.
AND and OR gates, FIG. 2, can be implemented using the equivalent combination of a NOR gate with an inverter in the NOR gate input lines and output line, respectively, as in FIG. 3. As shown in FIG. 4, a parallel NOR gate 40 is implemented simply by connecting, in parallel, one transistor (43, 44) for each specified NOR gate input line (41,42). Assuming a "true" ("logical one") input signal turns a transistor on, one true input signal causes current conduction through resistor R between the voltage supply V and ground, which causes the voltage at NOR output terminal 45 to drop from V to a "false" ("logical zero") level, regardless of the value of other input signals applied to other input leads of NOR gate 40. If all parallel transistors are off, current is blocked, causing a "true" level voltage at NOR gate output terminal 45.
Alternatively, a series NOR gate can be implemented as in FIG. 5 by connecting one transistor (53, 54) for each specified NOR gate input line (51, 52), in series with a resistor R, between a voltage supply V and a ground potential. If one input signal is true, then that signal, inverted by an inverter (56, 57) to "false" and applied to the control gate of a transistor, prevents conduction through resistor R, and causes a "false" output signal at the series NOR gate output terminal 55 regardless of other NOR input signal values. If the transistors (53, 54) are all ON, the series conducts current through resistor R, causing a "true" output signal on output terminal 55.
The switching speed of a transistor logic gate is that time for an output signal to be provided in response to a set of input signals. Signals flow through any number of parallel transistors simultaneously, in one delay interval, but flow through series transistors one after the other, adding delay intervals. In a series logic gate, the gate capacitance of a first transistor is charged in order to turn on that transistor, in turn charging the gate and diffusion capacitances and turning on each successive transistor, slowing signal propagation. A PLA gate using a large number of series transistors is significantly slower than one using the same transistors connected in parallel. Besides having more capacitance to charge, N transistors in series each need to have N times the cross sectional area of a transistor in a parallel path to transfer the same amount of current with the same voltage drop.
Causing current flow through a bias resistor to establish an output node voltage, whether in a parallel circuit as in FIG. 4 or in a series circuit as in FIG. 5, uses current, wasting power, which is uneconomical and dissipates heat. The transistors must be large so they can transfer enough current to cause a large voltage drop across the resistor.
Power and transistor space can be saved by precharging the capacitance of an output node to a selected voltage and, depending upon the state of the input signals, either maintaining or discharging the precharged voltage to establish the output signal voltage. In this manner current doen not flow in the "conductive stage" as in the non-precharged, resistive circuits of FIGS. 4 and 5.
FIG. 6 shows an example of a prior art precharged, parallel NOR gate 60. An enable transistor 66 is provided in ground line 16 and bias resistor R (of FIG. 4) is replaced with precharge transistor 15. A "precharge mode" is initiated by a high clock signal, which turns off ground line transistor 16 so that there is no path from output node 65 to ground, and also turns on precharge transistor 15. A pulse of precharge current charges the capacitance of output node 65. In a second, "output mode" initiated when the clock signal is low, precharge transistor 15 is turned off, and ground line transistor 16 is turned on. If either signal A or B is true, the corresponding transistor 63 or 64 is turned on, establishing a conductive path from precharged node 65 to ground, discharging node 65 to the low level "false" voltage. If neither A nor B is true, neither transistor 63 nor 64 establishes a path to ground, and node 65 is maintained at the high level "true" voltage.
The output node precharge value corresponds to the condition of no current flow through the bias resistor in a resistive gate as in FIGS. 4 and 5, as shown in Table I.
TABLE I ______________________________________ Output State Gate Series/ Corresponding Type Parallel to Non-conduction ______________________________________ OR Series True OR Parallel False NOR Series False NOR Parallel True AND Series False AND Parallel True NAND Series True NAND Parallel False ______________________________________
In a PLA where AND gate minterm output leads are connected to OR gate product term input leads, precharging AND gate output signals true tends to force OR gate output signals true, which is incompatible with precharging OR gate output leads false. In this event, as the "output mode" is initiated, a conflict exists between the precharged state of the AND and OR arrays, possibly resulting in false triggering of the OR gates. AND gate output leads precharged true can be isolated by transistor switches from incompatible OR gate input leads. However, this requires a multi-phase clock to delay turning on the switches to enable the OR gate input leads until the AND gate output leads have discharged and settled in response to the input signals, to avoid mistriggering OR gates. However, multi-phase clocks are an expense and inconvenience to be avoided.
There remains a need for a PLA circuit which reduces power consumption without using slow series gates or using OR input disabling transistors and a multi-phase clock, which occupy additional circuit area and make the integrated circuit more expensive.